1. Field of the Invention
The present invention relates to a clock generator for generating a clock into which jitter has been injected, a test apparatus for testing a device-under-test and an electronic device for outputting the clock into which jitter has been injected.
2. Related Art
Conventionally, a multi-phase clock is being used in high-speed data communication devices or serial I/O devices for the purpose of generating precisely timed bit intervals.
The multi-phase clock is generated by aligning phases of a plurality of low-frequency clocks so as to be evenly spaced from each other. For example, as the plurality of low-frequency clocks, signals outputted out of respective delay elements in a DLL (delay-locked loop) circuit or signals outputted out of respective inverters in a PLL (phase-locked loop) circuit are used.
There is also a jitter test among testing items for testing high-speed communication devices and the like. According to the recommendation of the International Telecommunication Union (ITU), the test must be carried out by injecting jitter having frequency of several 100 MHz into communication data for example.
However, a conventional multi-phase clock generator generates such multi-phase clock by aligning phases of low-frequency clocks so as to be evenly spaced by using the DLL, PLL or the like. Therefore, such multi-phase clock has had no jitter and could not be used for the jitter test. Still more, it has been difficult to inject high-frequency jitter into the high-frequency multi-phase clock after generating such high-frequency clock and hence it has been difficult to use the conventional multi-phase clock for the jitter test.
Accordingly, it is an object of the invention to provide a test apparatus and a clock generator capable of solving the above-mentioned problems. This object may be achieved through the combination of features described in independent claims of the invention. Dependent claims thereof specify preferable embodiments of the invention.